Lecture slides

Prelab and Lab exercises ("Lab 9" or first week of project) top_scomp Project Files Note the following after downloading the Project FIles above: The I/O timing for OUT described in Lab 8 has been replaced with simpler I/O timing for OUT. This simpler timing can be done with only Moore outputs, and it works with all I/O devices provided to you. You must simply ensure that your own I/O devices latch output data on the rising edge of IO_WRITE. You may note a similar Moore implementation of the MW output, which in no way changes the previous timing of MW. It is the same as described back in Lab 7, but is now done as a Moore assignment outside of the PROCESS. The ASM and MIF file provided are just simple placeholders that read the switches and write the value to the LEDs above them. The project should compile and work immediately in this respect, but you need to add your own MIF file to complete the Lab exercises and, later, your own project. When you view the Timing Analyzer results, you will see violations relative to the complex usage of CLOCK_50. You should be concerned only about your CLK_SCOMP (or whatever you end up calling it). In the timing analyzer results, CLK_SCOMP shows up as a reference to the clk0 output of your altpll instance (assuming you continue to use the clk0 output as in the examples). Watch out for setup violations of this clk0, or you will overclock your computer! Questions?? Ask them on the T-Square Forum, accessible through the T-Square site for ECE2031A. Students in the CS section have been granted access to the same forum on the 2031A section, but it has not been tested. Examples for Lab exercises: Keyboard Test from textbook Chapter 11 Mouse Test from textbook Chapter 11 Datasheets: DE2 Manual, including Pin Assignments Altera Cyclone Datasheet DE2 Schematics LCD Module (has some controller information, but look below) Better LCD Datasheet for controller IrDA Transceiver (Optics device -- FPGA controls encoding and decoding) Audio CODEC SRAM SDRAM Don't use Flash Memory RS-232 Transeiver (Level-converter only -- FPGA must implement UART) TV Decoder VGA DAC (Video DAC only -- FPGA must provide data, timed correctly) PS/2 Keyboard/Mouse protocol (See textbook Ch. 11 , too) DE2 resources: http://users.ece.gatech.edu/~hamblen/DE2/ DIRECT Link to the DE2 update files for the Hamblen textbook. Read the included README Notes on Porting UP3..... Revised Appendix C for lab manual with more pins. This is a subset of the information included in the DE2 manual above, but probably an easier way to find commonly-used pins. Needed at end of project: Peer Review Form If Peer Review Forms are NOT submitted by at least two members of a team, it will be assumed that team members were basically satisfied about the contributions of all. Forms can be submitted directly to your GTA electronically or by special arrangement to meet with him privately, but this should be done ASAP.